Hands-on experience with hardware verification methodologies and front-end design verification flows.
- Experience with HDL languages (SystemVerilog, Verilog) and verification frameworks (UVM/OVM).
- Experience with AI-powered development tools such as Claude, Claude Code, and MCP (Model Context Protocol) for automating and accelerating verification tasks.
- Proficiency in integrating LLM-based assistants into engineering workflows to improve productivity and code quality.
- Familiarity with machine learning concepts including supervised/unsupervised learning, neural networks, and their application to verification tasks (e.g., coverage closure, bug prediction, test generation).
- Building reusable verification components and libraries for future use.
- Candidate must have good analytical and problem-solving skills.
- Knowledge of simulation, debugging, and waveform analysis tools is good to have
- Knowledge of scripting languages (Python, Tcl, Perl) is good to have.
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